View ICM7218CIJIR5254_8995375.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

fn3159 rev 4.00 page 1 of 14 may 17, 2016 fn3159 rev 4.00 may 17, 2016 icm7218 8-digit led microprocessor-compatible multiplexed display decod er driver datasheet the icm7218 series of universal led dr iver systems provide, in a single package, all the circuitry necessary to interface most common microprocessors or digital systems to an led display. included on-chip are an 8-byte static display memory, two types of 7-segment decoders, multiplex scan circuitry, and high current digit and segment drivers for either common cathode or common anode displays. the lcm7218a and 1cm7218b feature two control lines (write and mode) which write either 4 bits of control information (data coming, shutdown , decode and hexa/code b ) or 8 bits of display input data. display data is automatically sequenced into the 8-byte internal memory on successive positive going write pulses. data may be displayed either directly or decoded in hexadecimal or code b formats. the icm7218c and lcm7218d feature two control lines (write and hexa/code b/shutdown ), 4 separate display data input lines, and 3 digit address lines. display data is written into the internal memory by setting up a digit address and strobing the write line low. only hexadecimal and code b formats are available for display outputs. features ? microprocessor compatible ? total circuit integrat ion on-chip includes: - digit and segment drivers - all multiplex scan circuitry - 8-byte static display memory - 7-segment hexadecimal and code b decoders ? output drive suitable for led displays directly ? common anode and common cathode versions ? single 5v supply required ? data retention to 2v supply ? shutdown feature - turns off display and puts chip into low power dissipation mode ? sequential and random access versions ? decimal point drive on each digit related literature ? technical brief tb363 , ?guidelines for handling and processing moisture sensitive surface mount devices (smds)? multiplex oscillator interdigit blanking 8-digit drivers 8-segment drivers decimal point 7 7 1 3 decode/ no-decode hexadecimal/ code b decoder 7 1 8 8 8 8 8 1 1 7 4 7 1 1 1 1 1 4 8 4 8 8 11 8 8 1 1 1 5 5 3 1 hexadecimal/ code b decoder multiplex oscillator 8-digit drivers 8-segment drivers decimal point interdigit blanking read adress, digit multiplexer read adress multiplexer write address decoder write address counter control logic 8-byte static ram 8-byte static ram three level input logic shutdown decode hexa/code b shutdown id0-id7 input data id4-id7 control inputs mode write hexadecimal/ code b/ shutdown write id0-id3 input data id7 da0-da2 digit address icm7218c common anode icm7218d common cathode icm7218a common anode icm7218b common cathode figure 1. functional diagrams
icm7218 fn3159 rev 4.00 page 2 of 14 may 17, 2016 ordering information part number part marking display type temp. range (c) package pkg. dwg. # icm7218aiji icm7218aiji common anode -40 to +85 28 ld cerdip f28.6 icm7218aijir5254 (note) icm7218aiji r5254 c ommon anode -40 to +85 28 ld cerdip f28.6 icm7218biji icm7218biji common cath ode -40 to +85 28 ld cerdip f28.6 icm7218bijir5254 (note) icm7218biji r5254 c ommon cathode -40 to +85 28 ld cerdip f28.6 icm7218ciji icm7218ciji common anode -40 to +85 28 ld cerdip f28.6 ICM7218CIJIR5254 (note) icm7218ciji r5254 common anode -40 to +85 28 ld cerdip f28.6 icm7218diji icm7218diji common cathode -40 to +85 28 ld cerdip f28.6 icm7218dijir5254 (note) (no longer available, recommended replacement: icm7218diji) icm7218diji r5254 common cathode -40 to +85 28 ld cerdip f28.6 note: these intersil pb-free hermetic packaged products employ a 1 00% matte tin plate plus anneal (e3) termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. ceramic dual in-line packaged products (cerdips) do contain lea d (pb) in the seal glass and die attach glass materials. however, lead in the glass mate rials of electronic components are currently exempted per the ro hs directive. therefore, ceramic dual inline packages with pb-free terminat ion finish are considered to be rohs compliant. pin configurations icm7218a (28 ld cerdip) top view icm7218b (28 ld cerdip) top view seg c seg e seg b d.p. id6 (hexa/codeb ) id5 (decode ) id7 (data coming) write mode id4 (shutdown ) id1 id0 id2 id3 v ss seg g seg d seg f digit 3 digit 7 v dd digit 8 digit 5 digit 2 digit 1 seg a digit 6 digit 4 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 digit 4 digit 6 digit 3 digit 1 id6 (hexa/codeb ) id5 (decode ) id7 (data coming) write mode id4 (shutdown ) id1 id0 id2 id3 v ss digit 5 digit 2 digit 8 seg g seg e v dd seg d seg b seg a d.p. digit 7 seg f seg c 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14
icm7218 fn3159 rev 4.00 page 3 of 14 may 17, 2016 icm7218c (28 ld cerdip) top view icm7218d (28 ld cerdip) top view pin configurations (continued) seg c seg e seg b d.p. da0 (digit address 0) da1 (digit address 1) id7 (input d.p. ) write hexa/code b/shutdown da2 (digit address 2) id1 id0 id2 id3 v ss seg g seg d seg f digit 3 digit 7 v dd digit 8 digit 5 digit 2 digit 1 seg a digit 6 digit 4 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 digit 4 digit 6 digit 3 digit 1 da0 (digit address 0) da1 (digit address 1) id7 (input d.p. ) write hexa/code b/shutdown da2 (digit address 2) id1 id0 id2 id3 v ss digit 5 digit 2 digit 8 seg g seg e v dd seg d seg b seg a d.p. digit 7 seg f seg c 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 input terminal logic level function icm7218a and icm7218b icm7218a icm7218b write 8 8 high input not loaded low input loaded mode 9 9 high load control bits on write pulse low load input data on write pulse id4 (shutdown ) mode high 10 10 high normal operation low shutdown (oscillator, decoder and display disabled) id5 (decode )66highno decode low decode id6 (hexa/code b ) 5 5 high hexadecimal decoding low code b decoding id7 (data coming) 7 7 high data coming no data coming low id0-id7 mode low 12, 11, 13, 14, 10, 6, 5, 7 12, 11, 13, 14, 10, 6, 5, 7 display data inputs ( notes 2 , 3 ) digit1 - digit8 15, 16, 23, 20, 17, 22, 21, 18 4, 25, 3, 1, 26, 2, 27, 24 digit driver outputs for com pin of 7 segment seg a, seg b, seg c, seg d, seg e, seg f, seg g, d.p. (digit point) 27, 3, 1, 25, 2, 24, 26, 4 16, 17, 20, 18, 21, 22, 23, 15 segment driver outputs for individual led pins of 7 segment v dd 19 19 power supply +5v v ss 28 28 supply ground icm7218c and icm7218d icm7218c icm7218d write 8 8 high input not loaded into memory low input loaded into memory } control word
icm7218 fn3159 rev 4.00 page 4 of 14 may 17, 2016 hexa/code b/ shutdown 9 ( note 1 )9 ( note 1 ) high hexadecimal decoding floating code b decoding low shutdown (oscillator, decoder and display disabled) da0 - da2 10, 6, 5 10, 6, 5 digit address inputs id0 - id3 14, 13, 11, 12 14, 13, 11, 12 display data inputs id7 (input d.p. ) 7 7 decimal point input digit1 - digit8 15, 16, 23, 20, 17, 22, 21, 18 4, 25, 3, 1, 26, 2, 27, 24 digit driver outputs for com pin of 7 segment seg a, seg b, seg c, seg d, seg e, seg f, seg g, d.p. (digit point) 27, 3, 1, 25, 2, 24, 26, 4 16, 17, 20, 18, 21, 22, 23, 15 segment driver outputs for individual led pins of 7 segment v dd 19 19 power supply +5v v ss 28 28 supply ground notes: 1. in the icm7218c and d (random access versions) the hexa/code b/shutdown input (pin 9) has internal biasing resistors to hold it at v dd /2 when pin 9 is open-circuited. these resistors consume power and result in a quiescent supply current (i q ) of typically 50a. the icm7218a and b devices do not have these biasing resistors and thus are not subject to this condition. 2. id0-id3 = don?t care when writing control data. id4-id6 = don?t care when writing hex/code b data. id7 = decimal point data. (the display blanks on icm7218a/b versions when writing in data). 3. in the no decode format, ?ones? represen ts ?on? segments for all inpu ts except for the decimal point, where ?zero? represents an ?on? segment (i.e., segments are positive true, de cimal point is negative true). 4. common anode segment drivers and common cathode digit drivers have 20k pull-up resistors. pin descriptions (continued) input terminal logic level function
icm7218 fn3159 rev 4.00 page 5 of 14 may 17, 2016 absolute maximum rating s thermal information supply voltage (v dd to v ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6v digit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300ma segment output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50ma input voltage (any terminal) ( note 5 ) . . . . . . . . . . v ss -0.3v to v dd + 0.3v operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c thermal resistance (typical, notes 6 , 7 ) ? ja (c/w) ? jc (c/w) cerdip package . . . . . . . . . . . . . . . . . . . . . 55 14 maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . . . . +300c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. due to the scr structure inherent in the cm0s process used to fabricate these devices, connecting any terminal to a voltage g reater than v dd or less than v ss may cause destructive device latch-up. for this reason it is re commended that no inputs from sources operating on a different power supply be applied to the device before its own supply is established, and when using multiple supply systems the supply to the icm7218 should be turned on first. 6. ? ja is measured with the component mounted on a low effective thermal conductivity test board in free air. see tech brief tb379 for details. 7. for ? jc , the ?case temp? location is the center of the ceramic on the package underside. electrical specifications v dd = 5v, v ss = 0v, t a = +25c, display diode drop = 1.7v symbol parameter test conditions min typ max unit v supply supply voltage range operating 4 - 6 v power down mode 2 - 6 v i q quiescent supply current shutdown ( note 1 ) 6 10 300 a i dd operating supply current - outputs open circuit common anode segs on ( note 4 )--2.5ma common anode segs off ( note 4 ) - - 500 a common cathode segs on ( note 4 ) - - 700 a common cathode segs off ( note 4 ) - - 500 a i dig digit drive current common anode v out = v dd -2.0v 140 200 - ma common cathode v out = v ss +1.0v 50 100 - ma i dlk digit leakage current - shutdown mode common anode v out = 2v - - 100 a common cathode v out = 5v - - 100 a i seg peak segment drive current common anode v out = v ss +1.0v 20 40 - ma common anode v out = v dd -2.0v -10 -20 - ma i slk segment leakage current - shutdown mode common anode v out = v dd --100a common cathode v out = v ss --100a f mux display scan rate per digit - 250 - hz v ih three level input (pin 9 icm7218c/d) logical ?1? input voltage hexadecimal 4.5 - - v v if floating input code b 2.0 - 3.0 v v il logical ?0? input voltage shutdown - - 0.4 v z in three level input impedance ( note 1 )-100-k v ih logical ?1? input voltage 3.5 - - v v il logical ?0? input voltage - - 0.8 v t wl write pulse width (low) 7218a, 7218b 550 400 - ns 7218c, 7218d 400 250 - ns t mh mode hold time 7218a, 7218b 150 - - ns
icm7218 fn3159 rev 4.00 page 6 of 14 may 17, 2016 t ms mode set-up time 7218a, 7218b 500 - - ns t ds data set-up time 500 - - ns t dh data hold time 7218a, 7218b 50 - - ns 7218c, 7218d 125 - - ns t as digital address set-up time 7218c, 7218d 500 - - ns t ah digital address hold time 7218c, 7218d 0 - - ns z in data input impedance 5-10pf gate capacitance - 10 10 - electrical specifications v dd = 5v, v ss = 0v, t a = +25c, display diode drop = 1.7v (continued) symbol parameter test conditions min typ max unit figure 2. multiplex timing (common cathode version) figure 3. segment assignments
icm7218 fn3159 rev 4.00 page 7 of 14 may 17, 2016 detailed description decode operation for the lcm7218a/b products, there are 3 input data formats possible; either direct segment and decimal point information (8 bits per digit) or two binary formats plus decimal point information (hexadecimal/code b fo rmats with 5 bits per digit). the 7-segment decoder on chip is disabled when direct segment information is to be written. in this format, the inputs directly control the outputs as follows: here, ?ones? represent ?on? segments for all inputs except the decimal point. for the decimal point ?zero? represents an ?on? segment. hexadecimal/code b decoding for all products, a choice of either hexa or code b decoding may be made. hexa decoding provides 7-segment numeric plus six alpha characters while code b provides a negative sign (-), a blank (for leading zero blanking), certain useful alpha characters and all numeric formats. the four bit binary code is set up on inputs ld3-ld0, and decimal point data is set up on id7. shutdown s hutdown performs several functions: it puts the device into a very low dissipation mode (typically 10a at v dd = 5v), turns off both the digit and segment driver s, and stops the multiplex scan oscillator (this is the only way the scan oscillator can be disabled). however, it is still possible to input data to the memory during shutdown - only the display output sections of the device are disabled in this mode. powerdown in the shutdown mode, the supply voltage may be reduced to 2v without data in memory being lost. however, data should not be written into memory if the supply voltage is less than 4v. output drive the common anode output drive is approximately 200ma per digit at a 12% duty cycle. with segment peak drive current of 40ma typically, this results in 5ma average drive. the common cathode drive capability is approx imately one-half that of the common anode drive. if high impedance led displays are used, the drive current will be correspondingly less. inter digit blanking a blanking time of approximately 10s occurs between digit strobes. this ensures that the segment information is correct before the next digit drive, thereby avoiding display ghosting. driving larger displays if a higher average drive current per digit is required, it is possible to connect digit drive outputs together. for example, by paralleling pairs of digit drivers together to drive a 4 digit display, 5ma average segment drive current can be obtained. power dissipation considerations assuming common anode drive at v dd = 5v and all digits on with an average of 5 segments driven per digit, the average current would be approximat ely 200ma. assuming a 1.8v drop across the led display, there will be a 3.2v drop across the icm7218. the device power dissipation will therefore be 640mw, rising to about 900mw, for all ?8? ?s displayed. caution: position device in system such that air can flow freely to provide maximum cooling. the common cathode dissipation is approximately on e-half that of the common anode dissipation. sequential addressing considerations (lcm7218a/b) the control instructions are read from the input bus lines if mode is high and write low. the instructions occur on 4 lines and are - decode /no decode, type of decode (if desired), shutdown/no shutdown and data comlng/not coming. after the control word has been written (with the data co ming instruction), display data can be written into memory with each successive negative going write pulse. after all 8-digit memory locations have been written to, additional transitions of the write input are ignored until a new control word is written. it is not possible to change one individual digit without refreshing the data for all the other digits. random access input drive considerations (icm7218c/d) control instructions are provided to the icm7218c/d by a single three level input terminal (pin 9), which operates independently of the write pulse. data can be written into memory on the lcm7218c/d by setting up a 3 bit binary code (one of eight) on the digit address inputs and applying a low level to the write pin. for example, it is possible to change only digit 7 without altering the data for the other digits (see figure 6 on page 8 ). supply capacitor a 0.1f plus a 47f capacitor is recommended between v dd and v ss to bypass display multiplexed noise. table 1. input data: id7 ld6 id5 ld4 ld3 ld2 ld1 id0 output segments: d.p. abcegfd table 2. decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 hexa code 01234567 8 9 a b c d e f code b 01234567 8 9 - e h l p (blank)
icm7218 fn3159 rev 4.00 page 8 of 14 may 17, 2016 figure 4. timing diagram for icm7218a/b figure 5. load sequence icm7218a/b figure 6. timing diagram for icm7218c/d 2
icm7218 fn3159 rev 4.00 page 9 of 14 may 17, 2016 figure 7. common anode displa y functional test circuit figure 8. common cathode display functional test circuit
icm7218 fn3159 rev 4.00 page 10 of 14 may 17, 2016 typical performance characteristics 0123 v out (volts) 0123 - v dd - v out (volts)
icm7218 fn3159 rev 4.00 page 11 of 14 may 17, 2016 application examples 8-digit microprocessor display application figure 9 shows a display interface using the lcm7218a/b with an 8048 family microcontroller. the 8 bit data bus (db0/db7-ld0/id7) transfers control and data information to the icm7218 display interface on successive write pulses. the mode input to the 7218 is connec ted to one of the i/o port pins on the microcontroller. when mode is high, a control word is transferred. when mode is low, data is transtered. sequential locations in the 8-byte static memory are automatically loaded on each successive write pulse. after eight write pulses have occurred, further pulses are ignored until a new control word is transferred (see figure 5 on page 8 ). this also allows writing to other peripheral devices without disturbing the lcm7218a/b. 16-digit microprocessor display in this application (see figure 10 on page 12 ), both lcm7218s are addressed simultaneously with a 3 bit word, da2-da0. display data from the 8048 i/o bus (db7-d80) is transferred to both lcm7218s simultaneously. the display digits from both lcm7218s are interleaved to allow adjacent pairs of digits to be loaded simultaneously from a single 8 bit data bus. decimal point information is supplied to the icm7218s from the processor on port lines p26 and p27. no decode application the lcm7218 can also be used as a microprocessor based led status panel driver. the microprocessor selected control word must include "no decode" and "data coming". the processor writes "ones" and "zeroes" into the lcm7218 which in turn directly drives appropriate discrete leds. led indicators can be red or green (8 segments x 8 digits = 64 dots/2 per red or green = 32 channels). figure 9. 8-digit microprocessor display
icm7218 fn3159 rev 4.00 page 12 of 14 may 17, 2016 figure 10. 16-digit display
icm7218 fn3159 rev 4.00 page 13 of 14 may 17, 2016 about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for in formational purposes only and is believ ed to be accurate, but not warranted. please go to the web to make sure that you have the latest revision. date revision change may 17, 2016 fn3159.4 applied intersil standards throughout datasheet. updated note in the ordering information table. updated pin configuration names on bottom two pin configurations. updated pin descriptions table on page 3. added note 7 on page 5. september 15, 2015 fn3159.3 updated ordering information table on page 2. added revision history and about intersil sections.
fn3159 rev 4.00 page 14 of 14 may 17, 2016 icm7218 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2001-2016. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. ceramic dual-in-line fr it seal packages (cerdip) notes: 1. index area: a notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead dimensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this configuration dimension b3 replaces dimension b2. 5. this dimension allows for of f-center lid, meniscus, and glass overrun. 6. dimension q shall be measured from the seating plane to the base plane. 7. measure dimension s1 at all four corners. 8. n is the maximum number of terminal positions. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling di mension: inch. bbb c a - b s c q l a seating base d plane plane -d- -a- -c- -b- ? d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 a m s s ccc c a - b m d s s aaa ca - b m d s s e a f28.6 mil-std-1835 gdip1-t28 (d-10, configuration a) 28 lead ceramic dual-in-line frit seal package symbol inches millimeters notes min max min max a - 0.232 - 5.92 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 1.490 - 37.85 5 e 0.500 0.610 12.70 15.49 5 e 0.100 bsc 2.54 bsc - ea 0.600 bsc 15.24 bsc - ea/2 0.300 bsc 7.62 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 6 s1 0.005 - 0.13 - 7 a90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2, 3 n28 288 rev. 0 4/94

▲Up To Search▲

Price & Availability of ICM7218CIJIR5254

	To Download ICM7218CIJIR5254 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .